Product Summary
The EP1K100QI208-1N provides a die-efficient, low-cost architecture by combining look-up table (LUT) architecture with EABs. LUT-based logic provides optimized performance and efficiency for data-path, register intensive, mathematical, or digital signal processing (DSP) designs, while EABs implement RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions. The element make EP1K100QI208-1N suitable for complex logic functions and memory functions such as digital signal processing, wide data-path manipulation, data transformation and microcontrollers, as required in high-performance communications applications. Based on reconfigurable CMOS SRAM elements, the EP1K100QI208-1N architecture incorporates all features necessary to implement common gate array megafunctions, along with a high pin count to enable an effective interface with system components. The advanced process and the low voltage requirement of the 2.5-V core allow EP1K100QI208-1N device to meet the requirements of low-cost, high-volume applications ranging from DSL modems to low-cost switches. The ability to reconfigure EP1K100QI208-1N enables complete testing prior to shipment and allows the designer to focus on simulation and design verification. The EP1K100QI208-1N reconfigurability eliminates inventory management for gate array designs and test vector generation for fault coverage.
Parametrics
EP1K100QI208-1N absolute maximum ratings: (1)VCCINT Supply voltage With respect to ground: –0.5~3.6 V; (2)VCCIO: –0.5~4.6 V; (3)VI DC input voltage: –2.0 5.75 V; (4)IOUT DC output current, per pin: –25~25 mA; (5)TSTG Storage temperature No bias: –65 150 ℃; (6)TAMB Ambient temperature Under bias: –65~135 ℃; (7)TJ Junction temperature PQFP, TQFP, and BGA packages, under bias: 135 ℃.
Features
EP1K100QI208-1N features: (1)Programmable logic devices (PLDs), providing low cost system-on-a-programmable-chip (SOPC) integration in a single device; (2)High density; (3)Cost-efficient programmable architecture for high-volume applications; (4)System-level features.
Diagrams
EP1K100FC256-1 |
IC ACEX 1K FPGA 100K 256-FBGA |
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EP1K100FC256-1N |
IC ACEX 1K FPGA 100K 256-FBGA |
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EP1K100FC256-2 |
IC ACEX 1K FPGA 100K 256-FBGA |
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EP1K100FC256-2N |
IC ACEX 1K FPGA 100K 256-FBGA |
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EP1K100FC256-3 |
IC ACEX 1K FPGA 100K 256-FBGA |
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EP1K100FC256-3N |
IC ACEX 1K FPGA 100K 256-FBGA |
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