XC2V3000-4FF1152I

Product Summary

The XC2V3000-4FF1152I is a platform FPGA developed for high performance from low-density to high-density designs that are based on IP cores and customized modules. The XC2V3000-4FF1152I delivers complete solutions for telecommunication, wireless, networking, video, and DSP applications, including PCI, LVDS, and DDR interfaces. The XC2V3000-4FF1152I leading-edge 0.15 μm / 0.12 μm CMOS 8-layer metal process and the Virtex-II architecture are optimized for high speed with low power consumption. Combining a wide variety of flexible features and a large range of densities up to 10 million system gates, the XC2V3000-4FF1152I enhances programmable logic design capabilities and is a powerful alternative to mask-programmed gates arrays. The XC2V3000-4FF1152I comprises 11 members, ranging from 40K to 8M system gates.

Parametrics

XC2V3000-4FF1152I absolute maximum ratings: (1)VCCINT, Internal supply voltage relative to GND: –0.5 to 1.65 V; (2)VCCAUX, Auxiliary supply voltage relative to GND: –0.5 to 4.0 V; (3)VCCO, Output drivers supply voltage relative to GND: –0.5 to 4.0 V; (4)VBATT, Key memory battery backup supply: –0.5 to 4.0 V; (5)VREF, Input reference voltage: –0.5 to VCCO + 0.5 V; (6)VIN, Input voltage relative to GND (user and dedicated I/Os): –0.5 to VCCO + 0.5 V; (7)VTS, Voltage applied to 3-state output (user and dedicated I/Os): –0.5 to 4.0 V; (8)TSTG, Storage temperature (ambient): –65 to +150℃.

Features

XC2V3000-4FF1152I features: (1)Up to 93,184 internal registers / latches with Clock; (2)Enable; (3)Up to 93,184 look-up tables (LUTs) or cascadable 16-bit shift registers; (4)Wide multiplexers and wide-input function support; (5)Horizontal cascade chain and Sum-of-Products support; (6)Internal 3-state bussing; (7)Fast SelectMAP. configuration; (8)Triple Data Encryption Standard (DES) security option (Bitstream Encryption); (9)IEEE1532 support; (10)Partial reconfiguration; (11)Unlimited re-programmability; (12)Readback capability; (13)Up to 1,108 user I/Os; (14)19 single-ended standards and six differential standards; (15)Programmable sink current (2 mA to 24 mA) per I/O; (16)Densities from 40K to 8M system gates; (17)420 MHz internal clock speed (Advance Data); (18)840+ Mb/s I/O (Advance Data).

Diagrams